Related S-Spec numbers
In addition to the SLA9U S-Spec, this processor was also manufactured with two pre-production S-Spec numbers:
NOTE: Engineering and qualifications samples are marked with this color
SLA9U CPUID information
| Intel Core 2 Duo E6850 SLA9U |
| Part number: |
HH80557PJ0804MG |
| Measured Frequency: |
3005 MHz |
|
| Comment: |
|
| Submitted by: |
xhoba |
|
|
General information
| Vendor: |
GenuineIntel |
| Processor name (BIOS): |
Intel(R) Core(TM)2 Duo CPU E6850 @ 3.00GHz |
| Cores: |
2 |
| Logical processors: |
2 |
| Processor type: |
Original OEM Processor |
| CPUID signature: |
6FB |
| Family: |
6 (06h) |
| Model: |
15 (0Fh) |
| Stepping: |
11 (0Bh) |
| TLB/Cache details: |
3rd-level cache: 4-MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0Fh, Model 06h), 2nd-level cache: 4-MB, 16-way set associative, 64-byte line size
64-byte Prefetching
Data TLB: 4-KB Pages, 4-way set associative, 256 entries
Data TLB: 4-MB Pages, 4-way set associative, 32 entries
Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries
L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries
L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries |
Cache details
| Cache: |
L1 data |
L1 instruction |
L2 |
| Size: |
2 x 32 KB |
2 x 32 KB |
4 MB |
| Associativity: |
8-way set
associative |
8-way set
associative |
16-way set
associative |
| Line size: |
64 bytes |
64 bytes |
64 bytes |
| Comments: |
Direct-mapped |
Direct-mapped |
Non-inclusive
Direct-mapped
Shared between all cores |
Supported instructions
| Instruction set extensions |
Additional instructions |
| MMX |
CLFLUSH |
| SSE |
CMOV |
| SSE2 |
CMPXCHG16B |
| SSE3 |
CMPXCHG8B |
| SSSE3 |
FXSAVE/FXRSTORE |
|
MONITOR/MWAIT |
|
SYSENTER/SYSEXIT |
Integrated features and technologies
| Major features |
Other features |
| On-chip Floating Point Unit |
36-bit page-size extensions |
| 64-bit / Intel 64 |
64-bit debug store |
| NX bit/XD-bit |
Advanced programmable interrupt controller |
| Intel Virtualization |
CPL qualified debug store |
| Intel Trusted Execution technology |
Debug store |
| Enhanced SpeedStep |
Debugging extensions |
|
Digital Thermal Sensor capability |
|
LAHF/SAHF support in 64-bit mode |
|
Machine check architecture |
|
Machine check exception |
|
Memory-type range registers |
|
Model-specific registers |
|
Page attribute table |
|
Page global extension |
|
Page-size extensions (4MB pages) |
|
Pending break enable |
|
Perfmon and Debug capability |
|
Physical address extensions |
|
Self-snoop |
|
Thermal monitor |
|
Thermal monitor 2 |
|
Thermal monitor and software controlled clock facilities |
|
Time stamp counter |
|
Virtual 8086-mode enhancements |
|
xTPR Update Control |
