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		Processor Intel Celeron 1.7 GHz Socket 478 SL68C (2e kans)	
€ 6,23 incl. BTW
            
            
            
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	Beschrijving
| 
 Dit is een 2e KANS artikel/product, en is getest op werking/functionaliteit! 
— GARANTIE 14 dagen na aankoop — 
| General information | 
 
| Type | 
CPU / Microprocessor | 
 
| Family | 
Intel Celeron | 
 
| Part number | 
BX80532RC2000B RK80532RC041128 | 
 
| Frequency (GHz)  ?  | 
2 | 
 
| Bus speed (MHz)  ?  | 
400 | 
 
| Clock multiplier  ?  | 
20 | 
 
| Package type | 
478-pin FC-PGA2 | 
 
| Socket type | 
Socket 478 (mPGA478B) | 
 
| Architecture / Microarchitecture / Other | 
 
| CPUID | 
0F27h | 
 
| Core stepping | 
C1 | 
 
| Processor core | 
Northwood-128 | 
 
| Manufacturing technology (micron) | 
0.13 | 
 
| Number of cores | 
1 | 
 
| L2 cache size (KB)  ?  | 
128 | 
 
| Core voltage (V)  ?  | 
1.25 – 1.525 | 
 
| Case temperature (°C)  ?  | 
68 | 
 
 
  
SL6RV CPUID information
| Intel Celeron 2.00 GHz SL6RV | 
 
| Part number: | 
RK80532RC041128 | 
 
| Measured Frequency: | 
 | 
 
 
 | 
| Comment: | 
 | 
 
| Submitted by: | 
Neon | 
 
 
 | 
 
|   | 
 
 
 
General information 
| Vendor: | 
GenuineIntel | 
 
| Processor name (BIOS): | 
Intel(R) Celeron(R) CPU 2.00GHz | 
 
| Logical processors: | 
1 | 
 
| Processor type: | 
Original OEM Processor | 
 
| CPUID signature: | 
F27 | 
 
| Family: | 
15 (0Fh) | 
 
| Model: | 
2 (02h) | 
 
| Stepping: | 
7 (07h) | 
 
| TLB/Cache details: | 
Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 128 entries No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache | 
 
 
Cache details 
| Cache: | 
L1 data | 
L1 instruction | 
L2 | 
 
| Size: | 
8 KB | 
12K uops | 
128 KB | 
 
| Associativity: | 
4-way set associative | 
8-way set associative | 
2-way set associative | 
 
| Line size: | 
64 bytes | 
  | 
64 bytes | 
 
| Comments: | 
sectored cache | 
  | 
sectored cache | 
 
 
 
Supported instructions 
| Instruction set extensions | 
Additional instructions | 
 
| MMX | 
CLFLUSH | 
 
| SSE | 
CMOV | 
 
| SSE2 | 
CMPXCHG8B | 
 
|   | 
FXSAVE/FXRSTORE | 
 
|   | 
SYSENTER/SYSEXIT | 
 
 
 
Integrated features and technologies 
| Major features | 
Other features | 
 
| On-chip Floating Point Unit | 
36-bit page-size extensions | 
 
|   | 
Advanced programmable interrupt controller | 
 
|   | 
Debug store | 
 
|   | 
Debugging extensions | 
 
|   | 
L1 context ID | 
 
|   | 
Machine check architecture | 
 
|   | 
Machine check exception | 
 
|   | 
Memory-type range registers | 
 
|   | 
Model-specific registers | 
 
|   | 
Page attribute table | 
 
|   | 
Page global extension | 
 
|   | 
Page-size extensions (4MB pages) | 
 
|   | 
Pending break enable | 
 
|   | 
Physical address extensions | 
 
|   | 
Self-snoop | 
 
|   | 
Thermal monitor | 
 
|   | 
Thermal monitor and software controlled clock facilities | 
 
|   | 
Time stamp counter | 
 
|   | 
Virtual 8086-mode enhancements | 
 
|   | 
xTPR Update Control | 
 
 
 
 
 
 
  
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