Processor Intel Celeron M 530 1.733 GHz Socket 478 SLA2G (2e kans)

Beschrijving

Dit is een 2e KANS artikel/product, en is getest op werking/functionaliteit! — GARANTIE 14 dagen na aankoop —

General information
Type	CPU / Microprocessor
Family	Intel Celeron M
Processor number  ?	530
Part number	LF80537NE0301MN BX80537530SR BX80537530T
Processor markings	LF80537 530 1.73/1M/553
Frequency  ?	1.733 GHz
Bus speed  ?	533 MHz
Clock multiplier  ?	13
Package type	478-pin Micro-FCPGA
Socket type	Socket P
Architecture / Microarchitecture / Other
CPUID	10661h
Core stepping	A1
Processor core	Merom
Manufacturing technology	0.065 micron
The number of cores	1
L2 cache size  ?	1 MB
Features	EM64T technology  ?  Execute disable bit  ?  MMX SSE SSE2 SSE3 SSSE3
Core voltage  ?	0.95V – 1.3V
Case temperature  ?	100°C
Thermal Design Power  ?	27 Watt
Notes on sSpec SLA2G
The part is discontinued. Last order date is April 16, 2010. Last shipment date for boxed processors is July 16, 2010. Last shipment date for OEM processors is October 15, 2010.

Related S-Spec numbers

In addition to the SLA2G S-Spec, this processor was also manufactured with a few production and pre-production S-Spec numbers:

Stepping	S-Spec	LF80537NE0301MN	BX80537530SR	BX80537530T	Unknown
A1	QVZO				+
	SLA2G	+	+	+
E1	SLA48	+

NOTE: Engineering and qualifications samples are marked with this color

Intel Celeron M 530 SLA2G
Part number:LF80537NE0301MNMeasured Frequency:1729 MHz	Comment:5737A378Submitted by:xhoba

General information

Vendor:	GenuineIntel
Processor name (BIOS):	Intel(R) Celeron(R) CPU 530 @ 1.73GHz
Cores:	1
Logical processors:	1
Processor type:	Original OEM Processor
CPUID signature:	10661
Family:	6 (06h)
Model:	22 (016h)
Stepping:	1 (01h)
TLB/Cache details:	64-byte Prefetching Data TLB: 4-KB Pages, 4-way set associative, 256 entries Data TLB: 4-MB Pages, 4-way set associative, 32 entries Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries

Cache details

Cache:	L1 data	L1 instruction	L2
Size:	32 KB	32 KB	1 MB
Associativity:	8-way set associative	8-way set associative	4-way set associative
Line size:	64 bytes	64 bytes	64 bytes
Comments:	Direct-mapped	Direct-mapped	Non-inclusive Direct-mapped

Supported instructions

Instruction set extensions		Additional instructions
MMX		CLFLUSH
SSE		CMOV
SSE2		CMPXCHG16B
SSE3		CMPXCHG8B
SSSE3		FXSAVE/FXRSTORE
		MONITOR/MWAIT
		SYSENTER/SYSEXIT

Integrated features and technologies

Major features		Other features
On-chip Floating Point Unit		36-bit page-size extensions
64-bit / Intel 64		64-bit debug store
NX bit/XD-bit		Advanced programmable interrupt controller
		CPL qualified debug store
		Debug store
		Debugging extensions
		Digital Thermal Sensor capability
		LAHF/SAHF support in 64-bit mode
		Machine check architecture
		Machine check exception
		Memory-type range registers
		Model-specific registers
		Page attribute table
		Page global extension
		Page-size extensions (4MB pages)
		Pending break enable
		Perfmon and Debug capability
		Physical address extensions
		Self-snoop
		Thermal monitor
		Thermal monitor 2
		Thermal monitor and software controlled clock facilities
		Time stamp counter
		Virtual 8086-mode enhancements
		xTPR Update Control