Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 64 entries No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache
Cache details
Cache:
L1 data
L1 instruction
L2
Size:
16 KB
12K uops
1 MB
Associativity:
8-way set associative
8-way set associative
8-way set associative
Line size:
64 bytes
64 bytes
Comments:
Direct-mapped
Non-inclusive Direct-mapped
Supported instructions
Instruction set extensions
Additional instructions
MMX
CLFLUSH
SSE
CMOV
SSE2
CMPXCHG8B
SSE3
FXSAVE/FXRSTORE
MONITOR/MWAIT
SYSENTER/SYSEXIT
Integrated features and technologies
Major features
Other features
On-chip Floating Point Unit
36-bit page-size extensions
Hyper-Threading Technology
64-bit debug store
Advanced programmable interrupt controller
CPL qualified debug store
Debug store
Debugging extensions
L1 context ID
Machine check architecture
Machine check exception
Memory-type range registers
Model-specific registers
Page attribute table
Page global extension
Page-size extensions (4MB pages)
Pending break enable
Physical address extensions
Self-snoop
Thermal monitor
Thermal monitor and software controlled clock facilities
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