Processor Intel Pentium Dual-Core E6500 2.933 GHz Socket 775 SLGUH (2e kans)

Beschrijving

Dit is een 2e KANS artikel/product, en is getest op werking/functionaliteit! — GARANTIE 14 dagen na aankoop —

General information
Type	CPU / Microprocessor
Family	Intel Pentium Dual-Core
Processor number  ?	E6500
Part number	AT80571PH0772ML BX80571E6500 BXC80571E6500
Frequency  ?	2.933 GHz
Bus speed  ?	1.066 GHz
Clock multiplier  ?	11
Package type	775-land FC-LGA8
Socket type	Socket 775 (LGA775)
Architecture / Microarchitecture / Other
CPUID	01067Ah
Core stepping	R0
Processor core	Wolfdale-3M
Manufacturing technology	0.045 micron
The number of cores	2
L2 cache size  ?	2 MB
Features	EM64T technology  ?  Enhanced SpeedStep technology  ?  Execute disable bit  ?  Extended Halt state Extended Stop Grant state Thermal Monitor 2 Virtualization technology
Core voltage  ?	0.85V – 1.3625V
Case temperature  ?	74.1°C
Thermal Design Power  ?	65 Watt
Notes on sSpec SLGUH
Deep Sleep low power mode is enabled.Deeper Sleep low power mode is enabled.The part is discontinued and will be offered only as an embedded processor. Last order date for non-embedded parts is August 26, 2011. Last shipment date for non-embedded OEM processors is February 10, 2012.

SLGUH CPUID information

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Intel Pentium Dual-Core E6500 SLGUH
Part number:AT80571PH0772MLMeasured Frequency:2940 MHz	Comment:Submitted by:xhoba

General information

Vendor:	GenuineIntel
Processor name (BIOS):	Pentium(R) Dual-Core CPU E6500 @ 2.93GHz
Cores:	2
Logical processors:	2
Processor type:	Original OEM Processor
CPUID signature:	1067A
Family:	6 (06h)
Model:	23 (017h)
Stepping:	10 (0Ah)
TLB/Cache details:	64-byte Prefetching Data TLB: 4-KB Pages, 4-way set associative, 256 entries Data TLB: 4-MB Pages, 4-way set associative, 32 entries Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries

Cache details

Cache:	L1 data	L1 instruction	L2
Size:	2 x 32 KB	2 x 32 KB	2 MB
Associativity:	8-way set associative	8-way set associative	8-way set associative
Line size:	64 bytes	64 bytes	64 bytes
Comments:	Direct-mapped	Direct-mapped	Non-inclusive Direct-mapped Shared between all cores

Supported instructions

Instruction set extensions		Additional instructions
MMX		CLFLUSH
SSE		CMOV
SSE2		CMPXCHG16B
SSE3		CMPXCHG8B
SSSE3		FXSAVE/FXRSTORE
		MONITOR/MWAIT
		SYSENTER/SYSEXIT
		XSAVE/XRESTORE states
		XSETBV/XGETBV are enabled

Integrated features and technologies

Major features		Other features
On-chip Floating Point Unit		36-bit page-size extensions
64-bit / Intel 64		64-bit debug store
NX bit/XD-bit		Advanced programmable interrupt controller
Intel Virtualization		CPL qualified debug store
Enhanced SpeedStep		Debug store
		Debugging extensions
		Digital Thermal Sensor capability
		LAHF/SAHF support in 64-bit mode
		Machine check architecture
		Machine check exception
		Memory-type range registers
		Model-specific registers
		Page attribute table
		Page global extension
		Page-size extensions (4MB pages)
		Pending break enable
		Perfmon and Debug capability
		Physical address extensions
		Self-snoop
		Thermal monitor
		Thermal monitor 2
		Thermal monitor and software controlled clock facilities
		Time stamp counter
		Virtual 8086-mode enhancements
		xTPR Update Control